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this document is a general product descripti on and is subject to change without notice. hynix semiconductor does not assume any responsibility for use of circuits described. no pat ent licenses are implied. rev. 1.0 / mar. 2005 1 512mb ddr sdram hy5du12422c(l)tp hy5du12822c(l)tp HY5DU121622C(l)tp
rev. 1.0 / mar. 2005 2 1 hy5du12422c(l)tp hy5du12822c(l)tp HY5DU121622C(l)tp revision history revision no. history draft date remark 1.0 first version release mar. 2005
rev. 1.0 / mar. 2005 3 1 hy5du12422c(l)tp hy5du12822c(l)tp HY5DU121622C(l)tp description the hy5du12422c(l)tp, hy5du12822c(l)tp and hy5du121622 c(l)tp are a 536,870,912-bit cmos double data rate(ddr) synchronous dram, ideally suited for the main memory applications which requires large memory density and high bandwidth. this hynix 512mb ddr sdrams offer fully synchronous operatio ns referenced to both rising and falling edges of the clock. while all addresses and control inputs are latched on the rising edges of the ck (f alling edges of the /ck), data, data strobes and write data masks inputs are sampled on both rising and falling edges of it. the data paths are inter- nally pipelined and 2-bit prefetched to achieve very high bandwidth. all input and output voltage levels are compatible with sstl_2. features ?v dd , v ddq = 2.5v 0.2v for ddr200, 266, 333 v dd , v ddq = 2.6v 0.1v for ddr400 ? all inputs and outputs are compatible with sstl_2 interface ? fully differential clock in puts (ck, /ck) operation ? double data rate interface ? source synchronous - data transaction aligned to bidirectional data strobe (dqs) ? x16 device has two bytewide data strobes (udqs, ldqs) per each x8 i/o ? data outputs on dqs edges when read (edged dq) data inputs on dqs centers when write (centered dq) ? on chip dll align dq and dqs transition with ck transition ? dm mask write data-in at the both rising and falling edges of the data strobe ? all addresses and control inputs except data, data strobes and data masks latched on the rising edges of the clock ? programmable cas latency 2/2.5 (ddr200, 266, 333) and 3 (ddr400) supported ? programmable burst length 2 / 4 / 8 with both sequential and interleave mode ? internal four bank operations with single pulsed /ras ? auto refresh and self refresh supported ? tras lock out function supported ? 8192 refresh cycles / 64ms ? jedec standard 400mil 66pin tsop-ii with 0.65mm pin pitch ? lead free (rohs* compliant) ordering information * x means speed grade part no. configuration package hy5du12422c(l)tp-x* 128m x 4 400mil 66pin tsop-ii (lead free) hy5du12822c(l)tp-x* 64m x 8 HY5DU121622C(l)tp-x* 32m x 16 operating frequency grade clock rate remark (cl-trcd-trp) -d43 200mhz@cl3 ddr400b (3-3-3) - j 133mhz@cl2 166mhz@cl2.5 ddr333 (2.5-3-3) - k 133mhz@cl2 133mhz@cl2.5 ddr266a (2-3-3) - h 100mhz@cl2 133mhz@cl2.5 ddr266b (2.5-3-3) - l 100mhz@cl2 ddr200 (2-2-2) *rohs (restriction of hazardous substance)
rev. 1.0 / mar. 2005 4 1 hy5du12422c(l)tp hy5du12822c(l)tp HY5DU121622C(l)tp pin configuration 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 vdd dq0 vddq dq1 dq2 vssq dq3 dq4 vddq dq5 dq6 vssq dq7 nc vddq ldqs nc vdd nc ldm /we /cas /ras /cs nc ba0 ba1 a10/ap a0 a1 a2 a3 vdd vss dq15 vssq dq14 dq13 vddq dq12 dq11 vssq dq10 dq9 vddq dq8 nc vssq udqs nc vref vss udm /ck ck cke nc a12 a11 a9 a8 a7 a6 a5 a4 vss vdd dq0 vddq nc dq1 vssq nc dq2 vddq nc dq3 vssq nc nc vddq nc nc vdd nc nc /we /cas /ras /cs nc ba0 ba1 a10/ap a0 a1 a2 a3 vdd vss dq7 vssq nc dq6 vddq nc dq5 vssq nc dq4 vddq nc nc vssq dqs nc vref vss dm /ck ck cke nc a12 a11 a9 a8 a7 a6 a5 a4 vss vdd nc vddq nc dq0 vssq nc nc vddq nc dq1 vssq nc nc vddq nc nc vdd nc nc /we /cas /ras /cs nc ba0 ba1 a10/ap a0 a1 a2 a3 vdd vss nc vssq nc dq3 vddq nc nc vssq nc dq2 vddq nc nc vssq dqs nc vref vss dm /ck ck cke nc a12 a11 a9 a8 a7 a6 a5 a4 vss x16 x8 x4 x4 x8 x16 400mil x 875mil 66pin tsop -ii 0.65mm pin pitch (lead free) row and column address table items 128mx4 64mx8 32mx16 organization 32m x 4 x 4banks 16m x 8 x 4banks 8m x 16 x 4banks row address a0 - a12 a0 - a12 a0 - a12 column address a0-a9, a11, a12 a0-a9, a11 a0-a9 bank address ba0, ba1 ba0, ba1 ba0, ba1 auto precharge flag a10 a10 a10 refresh 8k 8k 8k
rev. 1.0 / mar. 2005 5 1 hy5du12422c(l)tp hy5du12822c(l)tp HY5DU121622C(l)tp pin description pin type description ck, /ck input clock: ck and /ck are differen tial clock inputs. all address and control input signals are sampled on the crossing of the positive edge of ck and negative edge of /ck. output (read) data is referenced to the crossings of ck and /ck (both directions of crossing). cke input clock enable: cke high activa tes, and cke low deactivates internal clock signals, and device input buffers and output drivers. taking cke low provides precharge power down and self refresh operation (all ba nks idle), or active power down (row active in any bank). cke is synchronous for power down entry and exit, and for self refresh entry. cke is asynchronous for self refresh exit, and for output disable. cke must be maintained high throughout read and write accesses. input buffers, excluding ck, /ck and cke are disabled during powe r down. input buffers, excluding cke are disabled during self refresh. cke is an sstl_2 input, but will detect an lvcmos low level after vdd is applied. /cs input chip select: enables or disables all inputs except ck, /ck, cke, dqs and dm. all com- mands are masked when cs is registered high. cs provides for external bank selection on systems with multiple banks. cs is considered part of the command code. ba0, ba1 input bank address inputs: ba0 and ba1 define to which bank an active, read, write or pre- charge command is being applied. a0 ~ a12 input address inputs: provide the row address for active commands, and the column address and auto precharge bit for read/write commands, to select one location out of the memory array in the respective bank. a10 is sampled during a precharge command to determine whether the precharge applies to one bank (a10 low) or all banks (a10 high). if only one bank is to be precharg ed, the bank is selected by ba0, ba1. the address inputs also provide the op code during a mode register set command. ba0 and ba1 define which mode register is loaded during the mode register set command (mrs or emrs). /ras, /cas, /we input command inputs: /ras, /cas and /we (along with /cs) define the command being entered. dm (ldm,udm) input input data mask: dm is an input mask signal for write data. input data is masked when dm is sampled high al ong with that input data during a write access. dm is sampled on both edges of dqs. although dm pins ar e input only, the dm loading matches the dq and dqs loading. for the x16, ldm corresponds to the data on dq0-q7; udm corre- sponds to the data on dq8-q15. dqs (ldqs,udqs) i/o data strobe: output with read data, input with write data. edge aligned with read data, centered in write data. used to capture writ e data. for the x16, ldqs corresponds to the data on dq0-q7; udqs correspo nds to the data on dq8-q15. dq i/o data input / output pin: data bus v dd /v ss supply power supply for internal circuits and input buffers. v ddq /v ssq supply power supply for output buffers for noise immunity. v ref supply reference voltage for inputs for sstl interface. nc nc no connection.
rev. 1.0 / mar. 2005 6 1 hy5du12422c(l)tp hy5du12822c(l)tp HY5DU121622C(l)tp command decoder clk /clk cke /cs /ras /cas /we dm address buffer a0~a12 bank control 32mx4/bank0 column decoder column address counter sense amp 2-bit prefetch unit 32mx4/bank1 32mx4/bank2 32mx4/bank3 mode register row decoder input buffer output buffer dll block mode register data strobe transmitter data strobe receiver dqs clk /clk ds write data register 2-bit prefetch unit ds dq [0:3] 84 4 8 clk_dll ba0, ba1 functional block diagram (128mx4) 4banks x 32mbit x 4 i/o double data rate synchronous dram
rev. 1.0 / mar. 2005 7 1 hy5du12422c(l)tp hy5du12822c(l)tp HY5DU121622C(l)tp command decoder clk /clk cke /cs /ras /cas /we dm address buffer a0~a12 bank control 16mx8/bank0 column decoder column address counter sense amp 2-bit prefetch unit 16mx8/bank1 16mx8/bank2 16mx8/bank3 mode register row decoder input buffer output buffer dll block mode register data strobe transmitter data strobe receiver dqs clk /clk ds write data register 2-bit prefetch unit ds dq [0:7] 16 8 8 16 clk_dll ba0,ba1 functional block diagram (64mx8) 4banks x 16mbit x 8 i/o double data rate synchronous dram
rev. 1.0 / mar. 2005 8 1 hy5du12422c(l)tp hy5du12822c(l)tp HY5DU121622C(l)tp command decoder clk /clk cke /cs /ras /cas /we ldm address buffer a0~a12 bank control 8mx16/bank0 column decoder column address counter sense amp 2-bit prefetch unit 8mx16/bank1 8mx16/bank2 8mx16/bank3 mode register row decoder input buffer output buffer dll block mode register data strobe transmitter data strobe receiver ldqs, udqs clk /clk ldqs udqs write data register 2-bit prefetch unit ds dq[0:15] 32 16 16 32 clk_dll ba0, ba1 udm functional block diagram (32mx16) 4banks x 8mbit x 16 i/o double data rate synchronous dram
rev. 1.0 / mar. 2005 9 1 hy5du12422c(l)tp hy5du12822c(l)tp HY5DU121622C(l)tp simplified command truth table command cken-1 cken cs ras cas we addr a10/ap ba extended mode register set 1,2 hxllll op code mode register set 1,2 hxllll op code device deselect 1 hx hxxx x no operation 1 lhhh bank active 1 hxllhh ra v read 1 hxlhlhca l v read with autoprecharge 1,3 h write 1 hxlhllca l v write with autoprecharge 1,4 h precharge all banks 1,5 hxllhlx hx precharge selected bank 1 lv read burst stop 1 hxlhhl x auto refresh 1 hhlllh x self refresh 1 entry hllllh x exit lh hxxx lhhh precharge power down mode 1 entry hl hxxx x lhhh exit lh hxxx lhhh active power down mode 1 entry hl hxxx x lvvv exit l h x note: 1. ldm/udm states are don?t care. refer to below write mask truth table. 2. op code(operand code) consists of a0~a12 and ba0~ba1 used for mode register setting during extended mrs or mrs. before entering mode register set mode, all banks must be in a precharge state and mrs command can be issued after trp period from precharge command. 3. if a read with autoprecharge command is detected by memory component in ck(n), then there will be no command presented to activated bank until ck(n+bl/2+trp). 4. if a write with autoprecharge command is detected by memory component in ck(n), then there will be no command presented to activated bank until ck(n+bl/2+1+twr+trp). write recovery time(twr) is needed to guarantee that the last data has been completely written. 5. if a10/ap is high when precharge command being issued, ba0/ba1 are ignored and all banks are selected to be precharged. *for more information about truth table, refer to ?device operation? section in hynix website. ( h=logic high level, l=logic low level, x=don?t care, v=va lid data input, op code=operand code, nop=no operation )
rev. 1.0 / mar. 2005 10 1 hy5du12422c(l)tp hy5du12822c(l)tp HY5DU121622C(l)tp write mask truth table function cken-1 cken /cs, /ras, /cas, /we dm addr a10/ ap ba data write 1 hx x l x data-in mask 1 hx x h x note: 1. write mask command masks burst write data with reference to ld qs/udqs(data strobes) and it is not related with read data. in case of x16 data i/o, ldm and udm control lowe r byte(dq0~7) and upper byte(dq8~15) respectively.
rev. 1.0 / mar. 2005 11 1 hy5du12422c(l)tp hy5du12822c(l)tp HY5DU121622C(l)tp simplified state diagram mrs sref srex pden pdex act aref pdex pden bst read write write writeap writeap read readap readap pre(pall) pre(pall) pre(pall) command input automatic sequence idle auto refresh pre- charge power-up power applied mode register set power down write with autopre- charge power down write read with autopre- charge bank active read self refresh
rev. 1.0 / mar. 2005 12 1 hy5du12422c(l)tp hy5du12822c(l)tp HY5DU121622C(l)tp power-up sequence and device initialization ddr sdrams must be powered up and initialized in a pred efined manner. operational pr ocedures other than those specified may result in undefined operation. power must fi rst be applied to vdd, then to vddq, and finally to vref (and to the system vtt). vtt must be applied after vddq to avoid device latch-up, which may cause permanent dam- age to the device. vref can be applied anytime after vddq , but is expected to be nominally coincident with vtt. except for cke, inputs are not recognized as valid until after vref is applied. cke is an sstl_2 input, but will detect an lvcmos low level after vdd is applied. maintaining an lv cmos low level on cke during power-up is required to guarantee that the dq and dqs outputs will be in the high-z state, where they will remain until driven in normal oper- ation (by a read access). after all power supply and reference voltages are stable, and the clock is stable, the ddr sdram requires a 200us delay prior to applying an executable command. once the 200us delay has been satisfied, a deselect or nop command should be applied, and cke should be brought high. following the nop command, a precharg e all command should be applied. next a extended mode register set command should be issued for the ex tended mode register, to enable the dll, then a mode register set command should be issued for the mode re gister, to reset the dll, and to program the operating parameters. after the dll reset, txsrd(dll locking time) sh ould be satisfied for read command. after the mode reg- ister set command, a precharge all command should be a pplied, placing the device in the all banks idle state. once in the idle state, two auto refresh cycles must be performed. additionally, a mode register set command for the mode register, with the reset dll bit deactivated lo w (i.e. to program operating parameters without resetting the dll) must be performed. following these cycl es, the ddr sdram is ready for normal operation. 1. apply power - vdd, vddq, vtt, vref in the following po wer up sequencing and attemp t to maintain cke at lvc- mos low state. (all the other input pins may be undefined.) ? vdd and vddq are driven from a single power converter output. ? vtt is limited to 1.44v (ref lecting vddq(max)/2 + 50mv vref variation + 40mv vtt variation. ? vref tracks vddq/2. ? a minimum resistance of 42 ohms (22 ohm series resistor + 22 ohm parallel resistor - 5% tolerance) limits the input current from the vtt supply into any pin. ? if the above criteria cannot be met by the system desi gn, then the following sequen cing and voltage relation- ship must be adhered to during power up. 2. start clock and maintain stable clock for a minimum of 200usec. 3. after stable power and clock, apply nop condition and take cke high. 4. issue extended mode register set (emrs) to enable dll. 5. issue mode register set (mrs) to reset dll and set devi ce to idle state with bit a8=high. (an additional 200 cycles(txsrd) of clock are required for locking dll) 6. issue precharge commands for all banks of the device. 7. issue 2 or more auto refresh commands. 8. issue a mode register set command to initia lize the mode register with bit a8 = low voltage description sequencing voltage relationship to avoid latch-up vddq after or with vdd < vdd + 0.3v vtt after or with vddq < vddq + 0.3v vref after or with vddq < vddq + 0.3v
rev. 1.0 / mar. 2005 13 1 hy5du12422c(l)tp hy5du12822c(l)tp HY5DU121622C(l)tp power-up sequence code code code code code code code code code code code code code code code nop pre mrs emrs pre nop mrs aref act rd vdd vddq vtt vref /clk clk cke cmd dm addr a10 ba0, ba1 dqs dq's lvcmos low level tis tih tvtd t=200usec trp tmrd trp trfc tmrd txsrd* read non-read command power up vdd and ck stable precharge all emrs set mrs set reset dll (with a8=h) precharge all 2 or more auto refresh mrs set (with a8=l) * 200 cycle(txsrd) of ck are required (for dll locking) before read command tmrd
rev. 1.0 / mar. 2005 14 1 hy5du12422c(l)tp hy5du12822c(l)tp HY5DU121622C(l)tp mode register set (mrs) the mode register is used to store the various operating mo des such as /cas latency, addressing mode, burst length, burst type, test mode, dll reset. the mode register is pr ogramed via mrs command. this command is issued by the low signals of /ras, /cas, /cs, /we and ba0. this command can be issued only when all banks are in idle state and cke must be high at least one cycle before the mode regi ster set command can be issued. two cycles are required to write the data in mode register. during the mrs cycle, an y command cannot be issued. once mode register field is determined, the information will be he ld until reset by another mrs command. ba1 ba0 a12 a11 a10 a9 a8 a7 a6 a5 a4 a3 a2 a1 a0 0 0 operating mode cas latency bt burst length a2 a1 a0 burst length sequential interleave 0 0 0 reserved reserved 001 2 2 010 4 4 011 8 8 1 0 0 reserved reserved 1 0 1 reserved reserved 1 1 0 reserved reserved 1 1 1 reserved reserved a3 burst type 0 sequential 1interleave a6 a5 a4 cas latency 0 0 0 reserved 0 0 1 reserved 010 2 011 3 1 0 0 reserved 101 1.5 110 2.5 1 1 1 reserved ba0 mrs type 0mrs 1emrs a12~a9 a8 a7 a6~a0 operating mode 0 0 0 valid normal operation 0 1 0 valid normal operation/ reset dll 001vs vendor specific test mode ---- all other states reserved
rev. 1.0 / mar. 2005 15 1 hy5du12422c(l)tp hy5du12822c(l)tp HY5DU121622C(l)tp burst definition burst length & type read and write accesses to the ddr sdram are burst orient ed, with the burst length be ing programmable. the burst length determines the maximum number of column locations that can be acce ssed for a given read or write com- mand. burst lengths of 2, 4 or 8 locations are available for both the sequential and the interleaved burst types. reserved states should not be used, as unknown operatio n or incompatibility with future versions may result. when a read or write command is issued, a block of column s equal to the burst length is effectively selected. all accesses for that burst take place within this block, mean ing that the burst wraps within the block if a boundary is reached. the block is uniquely selected by a1-ai when the burst length is set to two, by a2 -ai when the burst length is set to four and by a3 -ai when the burst length is set to eight (where ai is the most significant column address bit for a given configuration). the remaining (least significant) a ddress bit(s) is (are) used to select the starting location within the block. the programmed burst leng th applies to both read and write bursts. accesses within a given burst may be programmed to be either sequential or interleaved; th is is referred to as the burst type and is selected via bit a3. the ordering of acce sses within a burst is determined by the burst length, the burst type and the starting column addres s, as shown in burst definition table cas latency the read latency or cas latency is the delay in clock cy cles between the registration of a read command and the availability of the first burst of output data. the latenc y can be programmed 2 or 2.5 clocks for ddr200/266/333 and 3 clocks for ddr400. if a read command is registered at clock edge n, and the latency is m clocks, the data is avail- able nominally coincident with clock edge n + m. reserved states should not be used as unknown operation or incompatibility with future versions may result. burst length starting address (a2,a1,a0) sequential interleave 2 xx0 0, 1 0, 1 xx1 1, 0 1, 0 4 x00 0, 1, 2, 3 0, 1, 2, 3 x01 1, 2, 3, 0 1, 0, 3, 2 x10 2, 3, 0, 1 2, 3, 0, 1 x11 3, 0, 1, 2 3, 2, 1, 0 8 000 0, 1, 2, 3, 4, 5, 6, 7 0, 1, 2, 3, 4, 5, 6, 7 001 1, 2, 3, 4, 5, 6, 7, 0 1, 0, 3, 2, 5, 4, 7, 6 010 2, 3, 4, 5, 6, 7, 0, 1 2, 3, 0, 1, 6, 7, 4, 5 011 3, 4, 5, 6, 7, 0, 1, 2 3, 2, 1, 0, 7, 6, 5, 4 100 4, 5, 6, 7, 0, 1, 2, 3 4, 5, 6, 7, 0, 1, 2, 3 101 5, 6, 7, 0, 1, 2, 3, 4 5, 4, 7, 6, 1, 0, 3, 2 110 6, 7, 0, 1, 2, 3, 4, 5 6, 7, 4, 5, 2, 3, 0, 1 111 7, 0, 1, 2, 3, 4, 5, 6 7, 6, 5, 4, 3, 2, 1, 0
rev. 1.0 / mar. 2005 16 1 hy5du12422c(l)tp hy5du12822c(l)tp HY5DU121622C(l)tp dll reset the dll must be enabled for normal operation. dll enable is required during power up initialization, and upon return- ing to normal operation after having disabled the dll for th e purpose of debug or evaluation. the dll is automatically disabled when entering self refresh oper ation and is automatically re-enabled upon exit of self refresh operation. any time the dll is enabled, 200 clock cycles must occur to al low time for the internal clock to lock to the externally applied clock before an any command can be issued. output driver impedance control the normal drive strength for all outputs is specified to be sstl_2, class ii. hynix also supports a half strength driver option, intended for lighter load and/or point-to-point envi ronments. selection of the half strength driver option will reduce the output drive strength by 50% of that of the full strength driver. i-v curves for both the full strength driver and the half strength driver are included in this document.
rev. 1.0 / mar. 2005 17 1 hy5du12422c(l)tp hy5du12822c(l)tp HY5DU121622C(l)tp extended mode register set (emrs) the extended mode register controls functions beyond thos e controlled by the mode register; these additional func- tions include dll enable/disable, output dr iver strength selection(optional). thes e functions are controlled via the bits shown below. the extended mode register is programmed via the mode register set command (ba0=1 and ba1=0) and will retain the stored information until it is programmed again or the device loses power. the extended mode register must be load ed when all banks are idle and no burs ts are in progress, and the controller must wait the specified time before initiating any subseque nt operation. violating either of these requirements will result in unspecified operation. ba1 ba0 a12 a11 a10 a9 a8 a7 a6 a5 a4 a3 a2 a1 a0 0 1 operating mode 0* ds dll a0 dll enable 0enable 1disable ba0 mrs type 0mrs 1emrs a1 output driver impedance control 0 full strength driver 1 half strength driver * this part do not support/qfc functi on, a2 must be programmed to zero. an~a3 a2~a0 operating mode 0valid normal operation __ all other states reserved
rev. 1.0 / mar. 2005 18 1 hy5du12422c(l)tp hy5du12822c(l)tp HY5DU121622C(l)tp absolute maximum ratings note: operation at above absolute maximum rating can adversely affect device reliability dc operating conditions (ta=0 to 70 o c, voltage referenced to v ss = 0v) note: 1. vddq must not exceed the level of vdd. 2. vil (min) is acceptable -1.5v ac pulse width with < 5ns of duration. 3. vref is expected to be equal to 0.5*vddq of the transmitting device, and to track variations in the dc level of the same. peak to peak noise on vref may not exceed 2% of the dc value. 4. vid is the magnitude of the difference between the input level on ck and the input level on /ck. 5. the ratio of the pullup current to the pulldown current is sp ecified for the same temperature and voltage, over the entire t emper- ature and voltage range, for devi ce drain to source voltages from 0.25v to 1.0v . for a given output, it represents the maximum dif- ference between pullup and pulldown drivers due to process variatio n. the full variation in the ratio of the maximum to minim um pullup and pulldown current will not exceed 1/7 for device drain to source voltages from 0.1 to 1.0. 6. vin=0 to vdd, all other pins are not tested under vin =0v. 7. dqs are disabled, vout=0 to vddq parameter symbol rating unit operating temperature (ambient) t a 0 ~ 70 o c storage temperature t stg -55 ~ 150 o c voltage on v dd relative to v ss v dd -1.0 ~ 3.6 v voltage on v ddq relative to v ss v ddq -1.0 ~ 3.6 v voltage on inputs relative to v ss v input -1.0 ~ 3.6 v voltage on i/o pins relative to v ss v io -0.5 ~3.6 v output short circuit current ios 50 ma soldering temperature ? time t solder 260 ? 10 o c ? sec parameter symbol min typ. max unit power supply voltage (ddr200, 266, 333) v dd 2.3 2.5 2.7 v power supply voltage (ddr200, 266, 333) 1 v ddq 2.3 2.5 2.7 v power supply voltage (ddr400) v dd 2.5 2.6 2.7 v power supply voltage (ddr400) 1 v ddq 2.5 2.6 2.7 v input high voltage v ih v ref + 0.15 - v ddq + 0.3 v input low voltage 2 v il -0.3 - v ref - 0.15 v termination voltage v tt v ref - 0.04 v ref v ref + 0.04 v reference voltage 3 v ref 0.49*vddq 0.5* vddq 0.51*vddq v input voltage level, ck and ck inputs vin(dc) -0.3 - vddq+0.3 v input differential voltage, ck and ck inputs 4 vid(dc) 0.36 - vddq+0.6 v v-i matching: pullup to pulldown current ratio 5 vi(ratio) 0.71 - 1.4 - input leakage current 6 i li -2 - 2 ua output leakage current 7 i lo -5 - 5 ua normal strength output driver (v out =vtt 0.84 ) output high current (min vddq, min vref, min vtt) ioh -16.8 - - ma output low current (min vddq, max vref, max vtt) iol 16.8 - - ma half strength output driver (v out =vtt 0.68 ) output high current (min vddq, min vref, min vtt) ioh -13.6 - - ma output low current (min vddq, max vref, max vtt) iol 13.6 - - ma
rev. 1.0 / mar. 2005 19 1 hy5du12422c(l)tp hy5du12822c(l)tp HY5DU121622C(l)tp idd specification and conditions (ta=0 to 70 o c, voltage referenced to v ss = 0v) test conditions test condition symbol operating current: one bank; active - precharge; trc= trc(min); tck=tck(min); dq,dm and dqs inputs changing twice per clock cycle; address and control inputs changing once per clock cycle idd0 operating current: one bank; active - read - precharge; burst length=2; trc=trc(min); tck=tck(min); address and control inputs changing once per clock cycle idd1 precharge power down standby current: all banks idle; power down mode; cke=low, tck=tck(min) idd2p idle standby current: vin>=vih(min) or vin==vih(min); all banks idle; cke>=vih(min); addresses and other control inputs stable, vin=vref for dq, dqs and dm idd2q active power down standby current: one bank active; power down mode; cke=low, tck=tck(min) idd3p active standby current: /cs=high; cke=high; one bank; active-pre charge; trc=tras(max); tck=tck(min); dq, dm and dqs inputs changi ng twice per clock cycle; address and other control inputs changing once per clock cycle idd3n operating current: burst=2; reads; continuous burst; one bank active; a ddress and control inputs changing once per clock cycle; tck=tck(min); iout=0ma idd4r operating current: burst=2; writes; continuous burst; one bank active; a ddress and control inputs changing once per clock cycle; tck=tck(min); dq, dm and dqs inputs changing twice per clock cycle idd4w auto refresh current: trc=trfc(min) - 8*tck for ddr200 at 100mhz, 10*tck for ddr266a & ddr266b at 133mhz; distributed refresh trc=trfc(min) - 14*tck for ddr400 at 200mhz idd5 self refresh current: cke =< 0.2v; external clock on; tck=tck(min) idd6 operating current - four bank operation: four bank interleaving with bl=4, refer to the following page for detailed test condition idd7
rev. 1.0 / mar. 2005 20 1 hy5du12422c(l)tp hy5du12822c(l)tp HY5DU121622C(l)tp idd specification 128mx4 64mx8 parameter symbol speed unit ddr400b ddr333 ddr266a ddr266b ddr200 operating current idd0 130 120 100 ma operating current idd1 170 150 120 ma precharge power down standby current idd2p 10 ma idle standby current idd2f 30 ma idle quiet standby current idd2q 25 ma active power down standby current idd3p 35 ma active standby current idd3n 50 ma operating current idd4r 200 180 160 ma operating current idd4w 230 210 180 auto refresh current idd5 245 225 205 self refresh current normal idd6 5ma low power 2.5 ma operating current - four bank operation idd7 400 350 290 ma parameter symbol speed unit ddr400b ddr333 ddr266a ddr266b ddr200 operating current idd0 130 120 100 ma operating current idd1 170 150 120 ma precharge power down standby current idd2p 10 ma idle standby current idd2f 30 ma idle quiet standby current idd2q 25 ma active power down standby current idd3p 35 ma active standby current idd3n 50 ma operating current idd4r 210 190 170 ma operating current idd4w 230 210 180 auto refresh current idd5 245 225 205 self refresh current normal idd6 5ma low power 2.5 ma operating current - four bank operation idd7 400 350 290 ma
rev. 1.0 / mar. 2005 21 1 hy5du12422c(l)tp hy5du12822c(l)tp HY5DU121622C(l)tp 32mx16 parameter symbol speed unit ddr400b ddr333 ddr266a ddr266b ddr200 operating current idd0 130 120 100 ma operating current idd1 170 150 120 ma precharge power down standby current idd2p 10 ma idle standby current idd2f 30 ma idle quiet standby current idd2q 25 ma active power down standby current idd3p 35 ma active standby current idd3n 50 ma operating current idd4r 210 190 170 ma operating current idd4w 280 240 220 auto refresh current idd5 245 225 205 self refresh current normal idd6 5ma low power 2.5 ma operating current - four bank operation idd7 400 350 290 ma
rev. 1.0 / mar. 2005 22 1 hy5du12422c(l)tp hy5du12822c(l)tp HY5DU121622C(l)tp detailed test conditions for ddr sdram idd1 & idd7 idd1: operating current: one bank operation 1. typical case: vdd = 2.5v, t=25 o c for ddr200, 266, 333; vdd = 2.6v, t=25 o c for ddr400 2. worst case: vdd = 2.7v, t= 0 o c 3. only one bank is accessed with trc(min), burst mode, address and control inputs on nop edge are changing once per clock cycle. lout = 0ma 4. timing patterns - ddr200(100mhz, cl=2): tck = 10ns, cl2, bl=2, trcd = 2*tck, trc = 10*tck, tras = 5*tck read: a0 n r0 n n p0 n a0 n - repeat the same timing with random address changing 50% of data changing at every burst - ddr266b(133mhz, cl=2.5): tck = 7.5ns, cl=2 .5, bl=4, trcd = 3*tck, trc = 9*tck, tras = 5*tck read: a0 n n r0 n p0 n n n a0 n - repeat the same timing with random address changing 50% of data changing at every burst - ddr266a (133mhz, cl=2): tck = 7.5ns, cl=2, bl=4, trcd = 3*tck, trc = 9*tck, tras = 5*tck read: a0 n n r0 n p0 n n n a0 n - repeat the same timing with random address changing 50% of data changing at every burst - ddr333(166mhz, cl=2.5): tck = 6ns, cl=2 , bl=4, trcd = 3*tck, trc = 10*tck, tras = 7*tck read: a0 n n r0 n n n p0 n n a0 n - re peat the same timing with random address changing 50% of data changing at every burst - ddr400(200mhz, cl=3): tck = 5ns, cl=3, bl=4, trcd = 3*tck, trc = 11*tck, tras = 8*tck read: a0 n n r0 n n n n p0 n n - repeat the same timing with random address changing 50% of data changing at every burst legend: a=activate, r=read, w=write, p=precharge, n=nop idd7: operating current: four bank operation 1. typical case: vdd = 2.5v, t=25 o c for ddr200, 266, 333; vdd = 2.6v, t=25 o c for ddr400 2. worst case: vdd = 2.7v, t= 0 o c 3. four banks are being interleaved with trc(min), burs t mode, address and control inputs on nop edge are not changing. lout = 0ma 4. timing patterns - ddr200(100mhz, cl=2): tck = 10ns, cl2, bl=4, trrd = 2*tck, trcd= 3*tck, read with autoprecharge read: a0 n a1 r0 a2 r1 a3 r2 a0 r3 a1 r0 - repeat the same timing with random address changing 50% of data changing at every burst - ddr266b(133mhz, cl=2.5): tck = 7.5ns, cl=2.5, bl =4, trrd = 2*tck, trcd = 3*tck read with autoprecharge read: a0 n a1 r0 a2 r1 a3 r2 n r3 a0 n a1 r0 - repeat the same timing with random address changing 50% of data changing at every burst - ddr266a (133mhz, cl=2): tck = 7.5ns, cl2=2, bl=4, trrd = 2*tck, trcd = 3*tck read: a0 n a1 r0 a2 r1 a3 r2 n r3 a0 n a1 r0 - repeat the same timing with random address changing 50% of data changing at every burst - ddr333(166mhz, cl=2.5): tck = 6ns, cl=2.5, bl=4, trrd = 2*tck, trcd = 3*tck, read with autoprecharge read: a0 n a1 r0 a2 r1 a3 r2 n r3 a0 n a1 r0 - repeat the same timing with random address changing 50% of data changing at every burst - ddr400(200mhz, cl=3): tck = 5ns, cl = 2, bl = 4, trrd = 2*tck, trcd = 3*tck, read with autoprecharge read: a0 n a1 r0 a2 r1 a3 r2 n r3 a0 n a1 r0 - repeat the same timing with random address changing 50% of data changing at every burst legend: a=activate, r=read, w=write, p=precharge, n=nop
rev. 1.0 / mar. 2005 23 1 hy5du12422c(l)tp hy5du12822c(l)tp HY5DU121622C(l)tp ac operating conditions (ta=0 to 70 o c, voltage referenced to v ss = 0v) note: 1. vid is the magnitude of the difference betw een the input level on ck and the input on /ck. 2. the value of vix is expected to equal 0.5*v ddq of the transmitting device and must track variations in the dc level of the same. *for more information about ac overshoot/undershoot specifications, refer to ?device operation? section in hynix website. ac operating test conditions (ta=0 to 70 o c, voltage referenced to vss = 0v) parameter symbol min max unit input high (logic 1) voltag e, dq, dqs and dm signals v ih(ac) v ref + 0.31 - v input low (logic 0) voltage, dq, dqs and dm signals v il(ac) -v ref - 0.31 v input differential voltage, ck and /ck inputs 1 v id(ac) 0.7 v ddq + 0.6 v input crossing point voltage, ck and /ck inputs 2 v ix(ac) 0.5*v ddq -0.2 0.5*v ddq +0.2 v parameter value unit reference voltage v ddq x 0.5 v termination voltage v ddq x 0.5 v ac input high level voltage (v ih , min) v ref + 0.31 v ac input low level voltage (v il , max) v ref - 0.31 v input timing measurement reference level voltage v ref v output timing measurement reference level voltage v tt v input signal maximum peak swing 1.5 v input minimum signal slew rate 1 v/ns te r m i n a t i o n re s i s t o r ( r t )50 series resistor (r s ) 25 w output load capacitance for access time measurement (c l )30pf
rev. 1.0 / mar. 2005 24 1 hy5du12422c(l)tp hy5du12822c(l)tp HY5DU121622C(l)tp ac characteristics (note: 1 - 9 / ac operating conditions unless otherwise noted) parameter symbol ddr400b ddr333 ddr266a ddr266b ddr200 unit min max min max min max min max min max row cycle time trc 55 - 60 - 65 - 65 - 70 - ns auto refresh row cycle time trfc 70 - 72 - 75 - 75 - 80 - ns row active time tras 40 70k 42 70k 45 120k 45 120k 50 120k ns active to read with auto precharge delay trap trcd or trasmin - trcd or trasmin - trcd or trasmin - trcd or trasmin - trcd or trasmin -ns row address to column address delay trcd 15 - 18 - 20 - 20 - 20 - ns row active to row active delay trrd 10 - 12 - 15 - 15 - 15 - ns column address to column address delay tccd1-1-1-1-1-tck row precharge time trp 15 - 18 - 20 - 20 - 20 - ns write recovery time twr 15 - 15 - 15 - 15 - 15 - ns internal write to read command delay twtr2-1-1-1-1-tck auto precharge write recovery + precharge time 22 tdal (twr/ tck) + (trp/tck) - (twr/ tck) + (trp/tck) - (twr/ tck) + (trp/tck) - (twr/ tck) + (trp/tck) - (twr/ tck) + (trp/tck) -tck system clock cycle time 24 cl = 3 tck 510-------- cl = 2.5 - - 6 12 7.5 12 7.5 12 8.0 12 ns cl = 2 - - 7.5127.51210121012ns clock high level width tch 0.45 0.55 0. 45 0.55 0.45 0.55 0.45 0.55 0.45 0.55 tck clock low level width tcl 0.45 0.55 0. 45 0.55 0.45 0.55 0.45 0.55 0.45 0.55 tck data-out edge to clock edge skew tac -0.7 0.7 -0.7 0.7 -0.75 0.75 -0.75 0.75 -0.75 0.75 ns dqs-out edge to clock edge skew tdqsck -0.55 0.55 -0.6 0.6 -0.75 0.75 -0.75 0.75 -0.75 0.75 ns dqs-out edge to data- out edge skew 21 tdqsq - 0.4 - 0.45 - 0.5 - 0.5 - 0.6 ns data-out hold time from dqs 20 tqh thp -tqhs - thp -tqhs - thp -tqhs - thp -tqhs - thp -tqhs -ns clock half period 19,20 thp min (tcl,tch) - min (tcl,tch) - min (tcl,tch) - min (tcl,tch) - min (tcl,tch) -ns data hold skew factor 20 tqhs - 0.5 - 0.55 - 0.75 - 0.75 - 0.75 ns valid data output window tdv tqh-tdqsq tqh-tdqsq tqh-tdqsq tqh-tdqsq tqh-tdqsq ns
rev. 1.0 / mar. 2005 25 1 hy5du12422c(l)tp hy5du12822c(l)tp HY5DU121622C(l)tp - continue parameter symbol ddr400b ddr333 ddr266a ddr266b ddr200 unit min max min max min max min max min max data-out high-impedance window from ck,/ck 10 thz -0.7 0.7 -0.7 0.7 -0.75 0.75 -0.75 0.75 -0.8 0.8 ns data-out low-impedance window from ck, /ck 10 tlz -0.7 0.7 -0.7 0.7 -0.75 0.75 -0.75 0.75 -0.8 0.8 ns input setup time (fast slew rate) 14,16-18 tis 0.6 - 0.75 - 0.9 - 0.9 - 1.1 - ns input hold time (fast slew rate) 14,16-18 tih 0.6 - 0.75 - 0.9 - 0.9 - 1.1 - ns input setup time (slow slew rate) 15-18 tis 0.7 - 0.8 - 1.0 - 1.0 - 1.1 - ns input hold time (slow slew rate) 15-18 tih 0.7 - 0.8 - 1.0 - 1.0 - 1.1 - ns input pulse width 17 tipw 2.2 - 2.2 - 2.2 - 2.2 - 2.5 - ns write dqs high level width tdqsh 0.35 - 0.35 - 0.35 - 0.35 - 0.35 - tck write dqs low level width tdqsl 0.35 - 0.35 - 0.35 - 0.35 - 0.35 - tck clock to first rising edge of dqs- in tdqss 0.72 1.25 0.75 1.25 0.75 1.25 0.75 1.25 0.75 1.25 tck dqs falling edge to ck setup time tdss 0.2 -0.2 -0.2 -0.2 -0.2 -tck dqs falling edge hold time from ck tdsh 0.2 -0.2 -0.2 -0.2 -0.2 -tck dq & dm input setup time 25 tds 0.4 - 0.45 - 0.5 - 0.5 - 0.6 - ns dq & dm input hold time 25 tdh 0.4 - 0.45 - 0.5 - 0.5 - 0.6 - ns dq & dm input pulse width 17 tdipw 1.75 - 1.75 - 1.75 - 1.75 - 2 - ns read dqs preamble time trpre 0.9 1.1 0.9 1.1 0.9 1.1 0.9 1.1 0.9 1.1 tck read dqs postamble time trpst 0.4 0.6 0.4 0.6 0.4 0.6 0.4 0.6 0.4 0.6 tck write dqs preamble setup time 12 twpres 0 -0-0- 0 -0 -ns write dqs preamble hold time twpreh 0.25 - 0.25 - 0.25 - 0.25 - 0.25 - tck write dqs postamble time 11 twpst 0.4 0.6 0.4 0.6 0.4 0.6 0.4 0.6 0.4 0.6 tck mode register set delay tmrd 2 -2-2- 2 -2 -tck exit self refresh to non-read command 23 txsnr 75 - 75 - 75 - 75 - 80 - ns exit self refresh to read command txsrd 200 - 200 - 200 - 200 - 200 - tck average periodic refresh interval 13,25 trefi - 7.8 - 7.8 - 7.8 - 7.8 - 7.8 us
rev. 1.0 / mar. 2005 26 1 hy5du12422c(l)tp hy5du12822c(l)tp HY5DU121622C(l)tp note: 1. all voltages referenced to vss. 2. tests for ac timing, idd, an d electrical, ac and dc characte ristics, may be conducted at nominal reference/supply voltage le vels, but the related specifications and device operation are guaranteed for the full voltage range specified. 3. below figure represents the timing refere nce load used in defining the relevant timing parameters of the part. it is not int ended to be either a precise representation of the typical system environment nor a depiction of the actual load pr esented by a producti on tester. system designers will use ibis or other simulation tools to correlate the timing referenc e load to a system environment . manufacturers will correlate to their production test conditions (generally a coaxial transmission line terminated at the teste r elec- tronics). 4. ac timing and idd tests may use a vil to vihswing of up to 1.5 v in the test environment, but input timing is still referenc ed to vref (or to the crossing point for ck, /ck) , and parameter specifications are guarante ed for the specified ac input levels unde r normal use conditions. the minimum slew rate for the input signals is 1 v/ns in the rang e between vil(ac) and vih(ac). 5. the ac and dc input level specifications are as defined in the sstl_2 standard (i.e ., the receiver will effectively switch a s a result of the signal crossing the ac in put level and will remain in that state as long as the signal does not ring back above (below) the dc input low (high) level. 6. inputs are not recognized as valid until vref stabilizes. exception: during the period before vref stabilizes, cke < 0.2vddq is recognized as low. 7. the ck, /ck input reference level (for timing referenced to ck , /ck) is the point at which ck and /ck cross; the input refer ence level for signals other than ck, /ck is vref. 8. the output timing reference voltage level is vtt. 9 . operation or timing that is not specified is illegal and after such an event, in order to guarantee proper operation, the dram must be powered down and then restarted through the specified initialization sequence before normal operation can continue. 10. thz and tlz transitions occur in the same access time windows as valid data transitions. these parameters are not reference d to a specific voltage level but specify when the device output is no longer driving (hz), or begins driving (lz). 11. the maximum limit for this parameter is not a device limit. the device will operate with a greater value for this parameter , but system performance (bus turnar ound) will degrade accordingly. 12. the specific requirement is that dqs be valid (high, low, or at some point on a valid transition) on or before this ck edge . a valid transition is defined as monotonic and meeting the input slew rate specifications of the device. when no writes were prev i- ously in progress on the bus, dqs will be transitioning from hi gh-z to logic low. if a previous write was in progress, dqs coul d be high, low, or transitioning from high to low at this time, depending on tdqss. 13. a maximum of eight auto refresh commands can be posted to any given ddr sdram device. 14. for command/address input slew rate 1.0 v/ns. 15. for command/address input slew rate 0.5 v/ns and 1.0 v/ns 16. for ck & / ck slew rate 1.0 v/ns (single-ended) 17. these parameters guarantee device timing, but they are not necessarily tested on each device. they may be guaranteed by device design or tester correlation. 18. slew rate is measured between voh(ac) and vol(ac). 19. min (tcl, tch) refers to the smaller of the actual clock low time and the actual clock high time as provided to the device (i.e. this value can be greater than the minimum specification limits for tcl and tch). for example, tcl and tch are = 50% of the period, less the half period jitter (tjit(hp)) of the clock source, and less th e half period jitter due to crosstalk (tjit(crosstalk)) into the clock traces. figure: timing reference load vddq 50 output (vout) 30 pf
rev. 1.0 / mar. 2005 27 1 hy5du12422c(l)tp hy5du12822c(l)tp HY5DU121622C(l)tp 20.tqh = thp - tqhs, where: thp = minimum half clock period for any given cycle and is defined by clock high or clock low (tch, tcl). tqhs accounts fo r 1) the pulse duration distortion of on-chip clock circuits; and 2) the worst case push--out of dqs on one transition followed by the worst case pull--in of dq on the next transition, both of which are, separately, due to data pin skew and output pattern effect s, and p-channel to n-channel vari ation of the output drivers. 21. tdqsq: consists of data pin skew and output pattern effects, and p-channel to n-channel variation of the output drivers for any g iven cycle. 22. tdal = (twr/tck) + (trp/tck) for each of the terms above, if not alre ady an integer, round to the next highest integer. example: for ddr266b at cl=2.5 and tck=7.5 ns tdal = ((15 ns / 7.5 ns) + (20 ns / 7.5 ns)) clocks = ((2) + (3)) clocks = 5 clocks 23. in all circumstances, txsnr can be satisfied using txsnr = trfcmin + 1*tck 24. the only time that the clock frequency is al lowed to change is duri ng self-refresh mode. 25. if refresh timing or tds/tdh is violated, data corruption may occur and the data must be re-written with valid data before a valid read can be executed.
rev. 1.0 / mar. 2005 28 1 hy5du12422c(l)tp hy5du12822c(l)tp HY5DU121622C(l)tp system characteristics conditions for ddr sdrams the following tables are described specification parameters that required in systems using ddr devices to ensure proper performannce. these characteristics are for system simulation purposes and are guaranteed by design. input slew rate for dq/dm/dqs (table a.) address & control input setup & hold time derating (table b.) dq & dm input setup & hold time derating (table c.) dq & dm input setup & hold time de rating for rise/fall delta slew rate (table d.) output slew rate characteris tics (for x4, x8 devices) (table e.) output slew rate character istics (for x16 device) (table f.) output slew rate matchi ng ratio characteristics (table g.) ac characteristics ddr400 ddr333 ddr266 ddr200 unit note parameter symbol min max min max min max min max dq/dm/dqs input slew rate measured between vih(dc), vil(dc) and vil(dc), vih(dc) dcslew 0.5 4.0 0.5 4.0 0.5 4.0 0.5 4.0 v/ns 1,12 input slew rate delta tis delta tih unit note 0.5 v/ns 0 0 ps 9 0.4 v/ns +50 0 ps 9 0.3 v/ns +100 0 ps 9 input slew rate delta tds delta tdh unit note 0.5 v/ns 0 0 ps 11 0.4 v/ns +75 0 ps 11 0.3 v/ns +150 0 ps 11 input slew rate delta tds delta tdh unit note 0.0 ns/v 00ps10 0.25 ns/v +50 +50 ps 10 0.5 ns/v +100 +100 ps 10 slew rate characteristic typical range (v/ ns) minimum (v/ns) maximum (v/ns) note pullup slew rate 1.2 - 2.5 1.0 4.5 1,3,4,6,7,8 pulldown slew rate 1.2 - 2.5 1.0 4.5 2,3,4,6,7,8 slew rate characteristic typical range (v/ ns) minimum (v/ns) maximum (v/ns) note pullup slew rate 1.2 - 2.5 1.0 4.5 1,3,4,6,7,8 pulldown slew rate 1.2 - 2.5 1.0 4.5 2,3,4,6,7,8 slew rate characteristic ddr266a ddr266b ddr200 note parameter min max min max min max output slew rate matching ratio (pullup to pulldown) - - - - 0.71 1.4 5,12
rev. 1.0 / mar. 2005 29 1 hy5du12422c(l)tp hy5du12822c(l)tp HY5DU121622C(l)tp note: 1. pullup slew rate is characterized under the test conditions as shown in below figure. 2. pulldown slew rate is measured under the test conditions shown in below figure. 3. pullup slew rate is measured between (vddq/2 - 320 mv 250mv) pulldown slew rate is measured between (vddq/2 + 320mv 250mv) pullup and pulldown slew rate conditions are to be met for any pattern of data, including all outputs switching and only on e output switching. example: for typical slew, dq0 is switching for minimum slew rate, all dq bits are switching worst case pattern for maximum slew rate, only one dq is switching from either high to low, or low to high. the remaining dq bi ts remain the same as for previous state. 4. evaluation conditions typical: 25 o c (ambient), vddq = no minal, typical process minimum: 70 o c (ambient), vddq = mini mum, slow-slow process maximum: 0 o c (ambient), vddq = maximum, fast-fast process 5. the ratio of pullup slew rate to pulldown slew rate is specified for the same temperature and voltage, over the entire tempe rature and voltage range. for a given output, it represents the maximum difference between pullup and pulldown drivers due to process variation. 6. verified under typical conditions for qualification purposes. 7. tsop-ii package devices only. 8. only intended for operation up to 256 mbps per pin. 9. a derating factor will be used to increase tis and tih in the case where the input slew rate is below 0.5 v/ns as shown in t able b. the input slew rate is based on the lesser of the slew rates dete rmined by either vih(ac) to vil(ac) or vih(dc) to vil(dc), sim - ilarly for rising transitions. 10. a derating factor will be used to increase tds and tdh in the case where dq, dm, and dqs slew rates differ, as shown in tab les c & d. input slew rate is based on the larger of ac-ac delta rise , fall rate and dc-dc delta rise, fall rate. input slew rate is based on the lesser of the slew rates determined by either vih(ac) to vil(ac) or vih(dc) to vil(dc), similarly for rising transitions. t he delta rise/fall rate is calculated as: {1/(slew rate1)} - {1/(slew rate2)} for example: if slew rate 1 is 0.5 v/ns and slew rate 2 is 0.4 v/ns , then the delta rise, fall rate is -0.5 ns/v. using the table given , this would result in the need for an in crease in tds and tdh of 100ps. 11. table c is used to increase tds and tdh in the case where th e i/o slew rate is below 0.5 v/ns . the i/o slew rate is based o n the lesser of the ac-ac slew rate and the dc-dc slew rate. the input slew rate is based on the lesser of the slew rates determined by either vih(ac) to vil(ac) or vih(dc) to vi l(dc), and similarly fo r rising transitions. 12. dqs, dm, and dq input slew rate is specified to prevent double clocking of data and preserve setup and hold times. signal t ran- sitions through the dc region must be monotonic. 50 output (vout) vssq test point figure: pullup slew rate vddq 50 test point output (vout) figure: pulldown slew rate
rev. 1.0 / mar. 2005 30 1 hy5du12422c(l)tp hy5du12822c(l)tp HY5DU121622C(l)tp capacitance (t a =25 o c, f=100mhz) note: 1. vdd = min. to max., vddq = 2.3v to 2.7v, v o dc = vddq/2, v o peak-to-peak = 0.2v 2. pins not under test are tied to gnd. 3. these values are guarant eed by design and are tested on a sample basis only. output load circuit parameter pin symbol min max unit input clock capacitance ck, /ck c i1 2.0 3.0 pf delta input clock capacitance ck, /ck delta c i1 -0.25pf input capacitance all other input-only pins c i1 2.0 3.0 pf delta input capacitance all other input-only pins delta c i2 -0.5pf input / output capacitance dq, dqs, dm c io 4.0 5.0 pf delta input / output capacitance dq, dqs, dm delta c io -0.5pf v ref v tt r t =50 ? zo=50 ? c l =30pf output
rev. 1.0 / mar. 2005 31 1 hy5du12422c(l)tp hy5du12822c(l)tp HY5DU121622C(l)tp package information 400mil 66pin thin sm all outline package 10.26 (0.404) 10.05 (0.396) 11.94 (0.470) 11.79 (0.462) 22.33 (0.879) 22.12 (0.871) 1.194 (0.0470) 0.991 (0.0390) 0.65 (0.0256) bsc 0.35 (0.0138) 0.25 (0.0098) 0.15 (0.0059) 0.05 (0.0020) base plane seating plane 0.597 (0.0235) 0.406 (0.0160) 0.210 (0.0083) 0.120 (0.0047) 0 ~ 5 deg. unit : mm(inch) max min ,

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